Some power semiconductor devices, such as reverse blocking IGBTs, high voltage inverse diodes, and high reverse blocking voltage thyristors, must be able to withstand high reverse voltages without suffering breakdown. Under high reverse voltages, a depletion region extends outward from a reverse biased junction in the active area of the device. If this depletion region, with its attendant high electric fields, were allowed to reach the side edges of the die, then breakdown and leakage may occur at the side edges of the die. For such high voltage bidirectional devices that are to withstand reverse voltages up to 3000 volts, a separation edge diffusion technology has been used. At the time of initial wafer processing, a first strip of aluminum is provided on the top of the N− type wafer so that the strip extends along what will be the ultimate edges of the device die. A second strip of aluminum is provided on the opposite side of the wafer, directly underneath the first strip. The two aluminum strips act as a diffusion sources. Under high temperature conditions, aluminum from these strips is made to diffuse into the wafer, thereby forming a downward extending P type region that extends downward from the top of the wafer, and thereby forming an upward extending P type region that extends upward from the bottom of the wafer. The two diffusion fronts of aluminum meet, thereby forming a single P type separation diffusion region that extends all the way from the top of the wafer, through the wafer, and to the bottom of the wafer. This separation diffusion region separates the active area of the device from what will be the die edge after singulation. The separation edge diffusion keeps the high electric fields of the reverse biased depletion region in the active area from reaching the sidewall edges of the die. For additional information on separation edge diffusion structures and techniques, see: 1) U.S. Pat. No. 7,442,630, entitled “Method For Fabricating Forward And Reverse Blocking Devices, filed Aug. 30, 2005, by Kelberlau et al.; 2) U.S. Pat. No. 5,698,454, entitled “Method Of Making A Reverse Blocking IGBT”, filed Jul. 31, 1995, by N. Zommer; and 3) J. Lutz et al., “Semiconductor Power Devices”, pages 146-147, published by Springer, Berlin and Heidelberg (2011).
For a bidirectional blocking device that is to withstand 3000 volts of reverse voltage, the wafer must be about 300 to 400 microns thick in order to provide enough silicon to contain the wide depletion region. The diffusion time required to form a separation edge diffusion through this wafer thickness is about 100 hours. If the separation edge diffusion technology is to be applied for blocking voltages over 3000 volts, then thicker silicon wafers are required. A rule of thumb is that about 100 microns more silicon in wafer thickness is required for each additional 1000 volts of blocking voltage. Diffusion depth, however, increases with the square root of diffusion time. So where the separation diffusion technique can be used to form separation diffusions through a 300 micron thick wafer in about 100 hours of diffusion time, doubling the wafer thickness to 600 microns would require a diffusion time equal to the square of the 100 hour diffusion time for the 300 micron thick wafer. The square of 100 hours of diffusion time is 10,000 hours. In addition, dopants of a very deep separation diffusion structure would diffuse laterally as well as vertically. The resulting large lateral extent of the separation diffusion structure would serve to consume an undesirably large amount of semiconductor die area. Accordingly, the extremely large amount of diffusion time and the undesirable large lateral dimension of the separation diffusion structure makes using the separation diffusion region technique commercially impractical for devices that are to have reverse blocking voltage ratings much in excess of 3000 volts.
Perhaps as a consequence of the impracticality of the separation edge diffusion technique mentioned above, the state of the art in the making of very high reverse voltage devices involves what are called bevel edge terminations. In bevel edge termination techniques, semiconductor material is removed at the upper peripheral edge of the die, thereby forming a so-called “bevel” at the upper peripheral edge of the die. In some technologies, this bevel edge is formed by mechanical grinding. In other techniques, the bevel edge is formed using etching techniques. For additional explanation of bevel edge termination techniques, see: B. Jayant Baliga, “Power Semiconductor Devices”, Chapter 3, pages 66-128, published by PWS Publishing Company, 20 Park Plaza, Boston, Mass. (1996). In one technique, a bevel edge is formed by etching a wide trench at what will be the die edge, where the sidewalls of the wide trench are sloped. For additional information, see: 1) U.S. Pat. No. 7,741,192, entitled “Semiconductor Device And manufacturing Method Thereof”, filed Aug. 19, 2005, by Shimoyama et al.; and 2) U.S. Pat. No. 7,776,672, entitled “Semiconductor Device And manufacturing Method Thereof”, filed Mar. 27, 2006, by Nakazawa et al. After the trench with the sloped sidewalls is formed, the wafer is singulated into dice by cutting, either using a saw or by laser cutting, down the center of the bottom of the trench. The sloped sidewall on one side of the trench forms the bevel edge of one die. The sloped sidewall on the opposite side of the trench forms the bevel edge of another die. In other bevel techniques, the semiconductor device is much larger and may, for example, when considered from the top-down perspective, be circular in shape. After the large area device die has been cut from the wafer, grinding and polishing processes are employed on the singulated circular dice in order to bevel the upper peripheral circular edges of the circular device. There are numerous other bevel edge termination techniques known in the art. Near ideal breakdown voltages are achievable using bevel edge termination techniques.